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001 10970
003 CUTN
005 20160328134048.0
006 m d
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008 110204e20110818njua s|||||||| 2|eng|d
020 _a9783642195679
020 _a3642195679 (Trade Cloth)
_cUSD 169.00 Retail Price (Publisher)
024 3 _a9783642195679
035 _a(WaSeSS)ssj0000610184
037 _a3642195679
_b00024965
040 _aBIP US
_dWaSeSS
_cCLC
050 4 _aTK7871.99.M44
082 0 0 _a621.39732
_223
210 1 0 _aLow Power and Reliable SRAM Memory Cell and Array Design
245 0 0 _aLow Power and Reliable SRAM Memory Cell and Array Design
_h[electronic resource]
_bedited by Koichiro Ishibashi and Kenichi Osada
260 _aNew York :
_bSpringer
_cAug. 2011
300 _axi, 143 p,
_c23 cm.
440 0 _aSpringer Series in Advanced Microelectronics Ser.
506 _aLicense restrictions may limit access.
520 8 _aAnnotation
_bThe recent development of advanced semiconductor device technologies is due to the success of SRAM memory cells. This book addresses issues in the design of SRAM memory cells for advanced CMOS technology, including variability, leakage and reliability.
521 _aScholarly & Professional
_bSpringer
700 1 _aIshibashi,Koichiro
_eEditor
_4edt
_zISH
700 1 _aOsada,Kenichi
_eEditor
_4edt
773 0 _tSpringerLink ebooks - Engineering (2011)
856 4 0 _uhttp://www.columbia.edu/cgi-bin/cul/resolve?clio9391361
_zFull text available from SpringerLink ebooks - Engineering (2011)
910 _aBowker Global Books in Print record
942 _2ddc
_cBOOKS
999 _c3174
_d3174